{"id":210,"date":"2026-03-04T12:24:00","date_gmt":"2026-03-04T12:24:00","guid":{"rendered":"https:\/\/primetoolhub.com\/?page_id=210"},"modified":"2026-07-12T09:37:28","modified_gmt":"2026-07-12T09:37:28","slug":"7400-series-ic-finder","status":"publish","type":"page","link":"https:\/\/schoolict.net\/tools\/7400-series-ic-finder\/","title":{"rendered":"7400 Series IC Finder &amp; Digital Logic Studio Pro"},"content":{"rendered":"\n<div class=\"pth-hero-section\">\n    <div class=\"pth-hero-content\">\n        <h2>Digital Logic Studio Pro<\/h2>\n        <p>Use Digital Logic Studio Pro to convert Boolean formulas to 7400\/4000 series ICs, generate NAND\/NOR universal forms and visualize SVG circuit diagrams \u2014 100% offline.<\/p>\n\n        <div id=\"pth-toc-placeholder\"><\/div>\n    <\/div>\n\n \n  <div class=\"pth-hero-image\">\n    <img data-no-lazy=\"1\"\n         src=\"https:\/\/schoolict.net\/tools\/wp-content\/uploads\/2026\/03\/Logic-Gate-Converter-800x447.jpeg\"\n         width=\"800\"\n         height=\"447\"\n         alt=\"7400 Series IC Finder\"\n         fetchpriority=\"high\"\n         loading=\"eager\"\n         decoding=\"async\"\n         style=\"width:100%; height:auto; display:block;\">\n  <\/div>\n<\/div>\n\n\n\n\n<div class=\"wp-block-rank-math-toc-block\" id=\"rank-math-toc\"><h2>Table of Contents<\/h2><nav><ul><li><a href=\"#\ud83d\udd34-ttl-or-cmos-making-the-right-call-before-you-order-parts\">\ud83d\udd34\u00a0TTL or CMOS? Making the Right Call Before You Order Parts<\/a><\/li><li><a href=\"#\ud83d\udfe1-what-the-pinout-diagram-is-actually-showing-you\">\ud83d\udfe1\u00a0What the Pinout Diagram Is Actually Showing You<\/a><\/li><li><a href=\"#\ud83d\udfe2-why-nand-and-nor-conversions-appear-on-every-analyzer-result\">\ud83d\udfe2\u00a0Why NAND and NOR Conversions Appear on Every Analyzer Result<\/a><\/li><li><a href=\"#\ud83d\udd34-reading-the-circuit-builder-diagram\">\ud83d\udd34\u00a0Reading the Circuit Builder Diagram<\/a><\/li><li><a href=\"#\ud83d\udfe1-getting-the-most-from-the-ic-library-tab\">\ud83d\udfe1\u00a0Getting the Most from the IC Library Tab<\/a><\/li><\/ul><\/nav><\/div>\n\n\n<!-- LSCACHE_DISABLE -->\r\n<style>\r\n#pth-ls3-wrapper{font-family:'Inter',system-ui,sans-serif;color:#1e293b;line-height:1.6;max-width:1400px;margin:0 auto;box-sizing:border-box;background:#f8fafc;padding:20px;border-radius:16px}\r\n#pth-ls3-wrapper *{box-sizing:border-box;min-width:0}\r\n#pth-ls3-wrapper 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.pth-toast.pth-ok{background:#047857}\r\n#pth-ls3-wrapper .pth-toast.pth-err{background:#991b1b}\r\n#pth-ls3-wrapper .pth-ic-count{font-size:.85rem;color:#334155;font-weight:700;padding:4px 0}\r\n@media(max-width:900px){#pth-ls3-wrapper .pth-grid2{grid-template-columns:1fr}}\r\n@media print{#pth-ls3-wrapper .pth-toolbar,#pth-ls3-wrapper .pth-tabs,#pth-ls3-wrapper .pth-input-row,#pth-ls3-wrapper .pth-quick-tags{display:none!important}}\r\n<\/style>\r\n\r\n<div id=\"pth-ls3-wrapper\">\r\n<div id=\"pth-ls3-toast\" class=\"pth-toast\" role=\"status\" aria-live=\"polite\"><\/div>\r\n\r\n<div class=\"pth-card\">\r\n  <h2 class=\"pth-title\">Digital Logic Studio Pro<\/h2>\r\n  <p class=\"pth-subtitle\">Boolean to IC converter, NAND\/NOR universal equivalents, SVG circuit builder, full 7400\/4000 series library &amp; Boolean laws reference. 100% offline.<\/p>\r\n  <div class=\"pth-meta\">\r\n    <span class=\"pth-badge pth-badge-blue\">v3.0<\/span>\r\n    <span class=\"pth-badge pth-green\">\ud83d\udd12 100% Offline<\/span>\r\n  <\/div>\r\n  <div class=\"pth-toolbar\">\r\n    <button type=\"button\" class=\"pth-btn pth-btn-purple\" id=\"pth-ls3-sample\">\ud83d\udca1 Load Sample<\/button>\r\n    <button type=\"button\" class=\"pth-btn pth-btn-sec\" id=\"pth-ls3-clear\">\ud83d\uddd1\ufe0f Clear All<\/button>\r\n  <\/div>\r\n<\/div>\r\n\r\n<div class=\"pth-card\">\r\n  <div class=\"pth-tabs\" role=\"tablist\" aria-label=\"Digital Logic Studio Pro sections\">\r\n    <button type=\"button\" class=\"pth-tab pth-active\" data-tab=\"analyzer\">\u26a1 Analyzer<\/button>\r\n    <button type=\"button\" class=\"pth-tab\" data-tab=\"circuit\">\ud83d\udd0c Circuit Builder<\/button>\r\n    <button type=\"button\" class=\"pth-tab\" data-tab=\"iclib\">\ud83d\udcdf IC Library<\/button>\r\n    <button type=\"button\" class=\"pth-tab\" data-tab=\"laws\">\ud83d\udcd0 Boolean Laws<\/button>\r\n    <button type=\"button\" class=\"pth-tab\" data-tab=\"history\">\ud83d\udd52 History<\/button>\r\n  <\/div>\r\n\r\n  <!-- ANALYZER TAB -->\r\n  <div id=\"pth-p-analyzer\" class=\"pth-panel pth-active\">\r\n    <div class=\"pth-input-row\">\r\n      <input type=\"text\" id=\"pth-ls3-formula\" class=\"pth-inp\" placeholder=\"e.g., (A AND B) OR (NOT C)\" aria-label=\"Boolean expression\">\r\n      <select id=\"pth-ls3-family\" class=\"pth-inp\" aria-label=\"IC family\">\r\n        <option value=\"TTL\">TTL 7400 Series (5V)<\/option>\r\n        <option value=\"CMOS\">CMOS 4000 Series (3-15V)<\/option>\r\n      <\/select>\r\n      <button type=\"button\" class=\"pth-btn pth-btn-primary\" id=\"pth-ls3-run\">\u26a1 Analyze<\/button>\r\n    <\/div>\r\n    <div class=\"pth-quick-tags\">\r\n      <span style=\"font-size:.78rem;font-weight:700;color:#334155;\">Quick:<\/span>\r\n      <span class=\"pth-tag\" data-f=\"A AND B\">AND<\/span>\r\n      <span class=\"pth-tag\" data-f=\"A OR B\">OR<\/span>\r\n      <span class=\"pth-tag\" data-f=\"NOT A\">NOT<\/span>\r\n      <span class=\"pth-tag\" data-f=\"A NAND B\">NAND<\/span>\r\n      <span class=\"pth-tag\" data-f=\"A NOR B\">NOR<\/span>\r\n      <span class=\"pth-tag\" data-f=\"A XOR B\">XOR<\/span>\r\n      <span class=\"pth-tag\" data-f=\"(A AND B) OR C\">Mixed<\/span>\r\n      <span class=\"pth-tag\" data-f=\"(A OR B) AND (C OR D)\">Complex<\/span>\r\n      <span class=\"pth-tag\" data-f=\"A AND B AND C\">3-input<\/span>\r\n    <\/div>\r\n    <div id=\"pth-ls3-err\" class=\"pth-error\" role=\"alert\" aria-live=\"assertive\"><\/div>\r\n    <div class=\"pth-cross-link\">\r\n      <p>\ud83d\udcca Need full truth table, equivalence checker or Verilog export?<\/p>\r\n      <a href=\"\/truth-table-generator\/\" target=\"_blank\" rel=\"noopener\">Truth Table Studio Pro \u2192<\/a>\r\n    <\/div>\r\n    <div class=\"pth-cross-link\" style=\"background:#f0fdf4;border-color:#bbf7d0;\">\r\n      <p>\ud83d\udd22 Need visual K-Map minimization or Quine-McCluskey reduction?<\/p>\r\n      <a href=\"\/advanced-k-map-solver\/\" target=\"_blank\" rel=\"noopener\">K-Map Solver \u2192<\/a>\r\n    <\/div>\r\n    <div id=\"pth-ls3-results\" class=\"pth-results\">\r\n      <div class=\"pth-grid2\">\r\n        <div>\r\n          <div class=\"pth-result-box\" style=\"margin-bottom:16px;\">\r\n            <p class=\"pth-rb-title\">Expression Analysis<\/p>\r\n            <div class=\"pth-info-row\"><span class=\"pth-lbl\">Readable form:<\/span><span class=\"pth-val\" id=\"pth-r-readable\"><\/span><\/div>\r\n            <div class=\"pth-info-row\"><span class=\"pth-lbl\">Symbolic:<\/span><span class=\"pth-val\" id=\"pth-r-sym\"><\/span><\/div>\r\n            <div class=\"pth-info-row\"><span class=\"pth-lbl\">Generator format:<\/span><span class=\"pth-val\" id=\"pth-r-gen\" style=\"color:#5b21b6;\"><\/span><\/div>\r\n            <div class=\"pth-info-row\"><span class=\"pth-lbl\">Variables:<\/span><span class=\"pth-val\" id=\"pth-r-vars\"><\/span><\/div>\r\n            <div class=\"pth-info-row\"><span class=\"pth-lbl\">Dominant gate:<\/span><span class=\"pth-val\" id=\"pth-r-gate\"><\/span><\/div>\r\n            <button type=\"button\" class=\"pth-btn pth-btn-sec\" style=\"width:100%;margin-top:10px;font-size:.82rem;padding:7px;\" id=\"pth-ls3-copy\">\ud83d\udccb Copy Generator Format<\/button>\r\n          <\/div>\r\n          <div class=\"pth-result-box\">\r\n            <p class=\"pth-rb-title\">Recommended IC<\/p>\r\n            <div class=\"pth-info-row\"><span class=\"pth-lbl\">Part number:<\/span><span id=\"pth-r-ic\" class=\"pth-ic-badge\">\u2014<\/span><\/div>\r\n            <div class=\"pth-info-row\"><span class=\"pth-lbl\">Gate config:<\/span><span class=\"pth-val\" id=\"pth-r-gates\"><\/span><\/div>\r\n            <div class=\"pth-info-row\"><span class=\"pth-lbl\">Package\/supply:<\/span><span class=\"pth-val\" id=\"pth-r-pwr\"><\/span><\/div>\r\n            <div class=\"pth-info-row\"><span class=\"pth-lbl\">Input count:<\/span><span class=\"pth-val\" id=\"pth-r-inputs\"><\/span><\/div>\r\n            <p class=\"pth-rb-title\" style=\"margin-top:14px;\">Universal Equivalents<\/p>\r\n            <p style=\"font-size:.78rem;font-weight:700;color:#334155;margin:0 0 4px;\">NAND-only form:<\/p>\r\n            <div class=\"pth-mono-dark\" id=\"pth-r-nand\"><\/div>\r\n            <p style=\"font-size:.78rem;font-weight:700;color:#334155;margin:4px 0;\">NOR-only form:<\/p>\r\n            <div class=\"pth-mono-dark\" id=\"pth-r-nor\"><\/div>\r\n          <\/div>\r\n        <\/div>\r\n        <div>\r\n          <div class=\"pth-result-box\">\r\n            <p class=\"pth-rb-title\">IC Pinout Diagram<\/p>\r\n            <div class=\"pth-pinout\" id=\"pth-r-pinout\"><\/div>\r\n            <p style=\"font-size:.75rem;color:#334155;font-weight:500;text-align:center;margin:10px 0 0;\">Educational pinout \u2014 always verify against the manufacturer datasheet before wiring.<\/p>\r\n          <\/div>\r\n        <\/div>\r\n      <\/div>\r\n    <\/div>\r\n    <div id=\"pth-ls3-empty\" class=\"pth-empty\">Enter a Boolean formula above and click Analyze to begin.<\/div>\r\n  <\/div>\r\n\r\n  <!-- CIRCUIT BUILDER TAB -->\r\n  <div id=\"pth-p-circuit\" class=\"pth-panel\">\r\n    <div class=\"pth-cross-link\">\r\n      <p>\u2139\ufe0f Circuit diagram auto-updates after each Analyzer run. Enter a formula in the Analyzer tab first.<\/p>\r\n      <a href=\"#\" id=\"pth-go-analyzer\">Go to Analyzer \u2192<\/a>\r\n    <\/div>\r\n    <div class=\"pth-svg-wrap\" id=\"pth-circuit-svg\">\r\n      <div class=\"pth-svg-empty\">Run an analysis in the Analyzer tab to generate the circuit diagram here.<\/div>\r\n    <\/div>\r\n    <button type=\"button\" class=\"pth-btn pth-btn-sec\" id=\"pth-circuit-dl\" style=\"display:none;\">\u2b07\ufe0f Download SVG<\/button>\r\n    <p style=\"font-size:.8rem;color:#334155;font-weight:500;margin-top:10px;\">Simplified gate-level schematic. Complex nested expressions show up to 3 gate levels.<\/p>\r\n  <\/div>\r\n\r\n  <!-- IC LIBRARY TAB -->\r\n  <div id=\"pth-p-iclib\" class=\"pth-panel\">\r\n    <div class=\"pth-ic-search-row\">\r\n      <input type=\"text\" id=\"pth-ic-search\" class=\"pth-ic-search\" placeholder=\"Search IC number or description...\" aria-label=\"Search IC library\">\r\n      <select id=\"pth-ic-family\" class=\"pth-inp\" style=\"flex-grow:0;min-width:160px;\" aria-label=\"Filter by family\">\r\n        <option value=\"ALL\">All Families<\/option>\r\n        <option value=\"TTL\">TTL 7400 Series<\/option>\r\n        <option value=\"CMOS\">CMOS 4000 Series<\/option>\r\n      <\/select>\r\n      <select id=\"pth-ic-gate\" class=\"pth-inp\" style=\"flex-grow:0;min-width:160px;\" aria-label=\"Filter by gate type\">\r\n        <option value=\"ALL\">All Gate Types<\/option>\r\n        <option value=\"AND\">AND<\/option>\r\n        <option value=\"OR\">OR<\/option>\r\n        <option value=\"NOT\">NOT \/ Inverter<\/option>\r\n        <option value=\"NAND\">NAND<\/option>\r\n        <option value=\"NOR\">NOR<\/option>\r\n        <option value=\"XOR\">XOR<\/option>\r\n        <option value=\"XNOR\">XNOR<\/option>\r\n        <option value=\"BUFFER\">Buffer<\/option>\r\n      <\/select>\r\n    <\/div>\r\n    <div class=\"pth-ic-count\" id=\"pth-ic-count\">Loading...<\/div>\r\n    <div class=\"pth-ic-grid\" id=\"pth-ic-grid\"><\/div>\r\n  <\/div>\r\n\r\n  <!-- BOOLEAN LAWS TAB -->\r\n  <div id=\"pth-p-laws\" class=\"pth-panel\">\r\n    <div id=\"pth-laws-applied\" style=\"margin-bottom:16px;\"><\/div>\r\n    <div class=\"pth-law-grid\" id=\"pth-law-grid\"><\/div>\r\n  <\/div>\r\n\r\n  <!-- HISTORY TAB -->\r\n  <div id=\"pth-p-history\" class=\"pth-panel\">\r\n    <div style=\"display:flex;justify-content:space-between;align-items:center;margin-bottom:14px;\">\r\n      <span style=\"font-weight:800;color:#0f172a;\">Session History<\/span>\r\n      <button type=\"button\" class=\"pth-btn pth-btn-danger\" style=\"padding:6px 12px;font-size:.78rem;\" id=\"pth-hist-clear\">Clear<\/button>\r\n    <\/div>\r\n    <div class=\"pth-hist-list\" id=\"pth-hist-list\">\r\n      <div class=\"pth-empty\">No history yet \u2014 run an analysis to begin.<\/div>\r\n    <\/div>\r\n    <p style=\"font-size:.78rem;color:#334155;font-weight:500;margin-top:12px;\">History is stored in memory only and clears when you reload the page.<\/p>\r\n  <\/div>\r\n<\/div>\r\n<\/div>\r\n<script data-no-optimize=\"1\" data-no-minify=\"1\" data-cfasync=\"false\">\r\n(function(){\r\n'use strict';\r\nif(window.pthLS3App){return;}\r\nwindow.pthLS3App={\r\ninitialized:false,\r\nhistory:[],\r\ncurrentAST:null,\r\ncurrentVars:[],\r\ncurrentSVG:'',\r\ncurrentFormat:'',\r\n\r\nIC_DB:[\r\n{ic:'7400',fam:'TTL',gate:'NAND',inputs:2,count:4,pkg:'14-pin DIP',vcc:'5V',desc:'Quadruple 2-input NAND gates'},\r\n{ic:'7402',fam:'TTL',gate:'NOR',inputs:2,count:4,pkg:'14-pin DIP',vcc:'5V',desc:'Quadruple 2-input NOR gates'},\r\n{ic:'7404',fam:'TTL',gate:'NOT',inputs:1,count:6,pkg:'14-pin DIP',vcc:'5V',desc:'Hex inverters (NOT gates)'},\r\n{ic:'7408',fam:'TTL',gate:'AND',inputs:2,count:4,pkg:'14-pin DIP',vcc:'5V',desc:'Quadruple 2-input AND gates'},\r\n{ic:'7410',fam:'TTL',gate:'NAND',inputs:3,count:3,pkg:'14-pin DIP',vcc:'5V',desc:'Triple 3-input NAND gates'},\r\n{ic:'7411',fam:'TTL',gate:'AND',inputs:3,count:3,pkg:'14-pin DIP',vcc:'5V',desc:'Triple 3-input AND gates'},\r\n{ic:'7420',fam:'TTL',gate:'NAND',inputs:4,count:2,pkg:'14-pin DIP',vcc:'5V',desc:'Dual 4-input NAND gates'},\r\n{ic:'7421',fam:'TTL',gate:'AND',inputs:4,count:2,pkg:'14-pin DIP',vcc:'5V',desc:'Dual 4-input AND gates'},\r\n{ic:'7425',fam:'TTL',gate:'NOR',inputs:4,count:2,pkg:'16-pin DIP',vcc:'5V',desc:'Dual 4-input NOR gates'},\r\n{ic:'7427',fam:'TTL',gate:'NOR',inputs:3,count:3,pkg:'14-pin DIP',vcc:'5V',desc:'Triple 3-input NOR gates'},\r\n{ic:'7430',fam:'TTL',gate:'NAND',inputs:8,count:1,pkg:'14-pin DIP',vcc:'5V',desc:'Single 8-input NAND gate'},\r\n{ic:'7432',fam:'TTL',gate:'OR',inputs:2,count:4,pkg:'14-pin DIP',vcc:'5V',desc:'Quadruple 2-input OR gates'},\r\n{ic:'7486',fam:'TTL',gate:'XOR',inputs:2,count:4,pkg:'14-pin DIP',vcc:'5V',desc:'Quadruple 2-input XOR gates'},\r\n{ic:'4000',fam:'CMOS',gate:'NOR',inputs:3,count:2,pkg:'14-pin DIP',vcc:'3-15V',desc:'Dual 3-input NOR + single NOT gate'},\r\n{ic:'4001',fam:'CMOS',gate:'NOR',inputs:2,count:4,pkg:'14-pin DIP',vcc:'3-15V',desc:'Quadruple 2-input NOR gates'},\r\n{ic:'4002',fam:'CMOS',gate:'NOR',inputs:4,count:2,pkg:'14-pin DIP',vcc:'3-15V',desc:'Dual 4-input NOR gates'},\r\n{ic:'4009',fam:'CMOS',gate:'NOT',inputs:1,count:6,pkg:'16-pin DIP',vcc:'3-15V',desc:'Hex inverting buffer\/converter'},\r\n{ic:'4010',fam:'CMOS',gate:'BUFFER',inputs:1,count:6,pkg:'16-pin DIP',vcc:'3-15V',desc:'Hex non-inverting buffer'},\r\n{ic:'4011',fam:'CMOS',gate:'NAND',inputs:2,count:4,pkg:'14-pin DIP',vcc:'3-15V',desc:'Quadruple 2-input NAND gates'},\r\n{ic:'4012',fam:'CMOS',gate:'NAND',inputs:4,count:2,pkg:'14-pin DIP',vcc:'3-15V',desc:'Dual 4-input NAND gates'},\r\n{ic:'4023',fam:'CMOS',gate:'NAND',inputs:3,count:3,pkg:'14-pin DIP',vcc:'3-15V',desc:'Triple 3-input NAND gates'},\r\n{ic:'4025',fam:'CMOS',gate:'NOR',inputs:3,count:3,pkg:'14-pin DIP',vcc:'3-15V',desc:'Triple 3-input NOR gates'},\r\n{ic:'4030',fam:'CMOS',gate:'XOR',inputs:2,count:4,pkg:'14-pin DIP',vcc:'3-15V',desc:'Quadruple 2-input XOR gates'},\r\n{ic:'4049',fam:'CMOS',gate:'NOT',inputs:1,count:6,pkg:'16-pin DIP',vcc:'3-15V',desc:'Hex inverter\/buffer (level shifting capable)'},\r\n{ic:'4050',fam:'CMOS',gate:'BUFFER',inputs:1,count:6,pkg:'16-pin DIP',vcc:'3-15V',desc:'Hex non-inverting buffer (level shifting)'},\r\n{ic:'4069',fam:'CMOS',gate:'NOT',inputs:1,count:6,pkg:'14-pin DIP',vcc:'3-15V',desc:'Hex inverter (low power, high gain)'},\r\n{ic:'4070',fam:'CMOS',gate:'XOR',inputs:2,count:4,pkg:'14-pin DIP',vcc:'3-15V',desc:'Quadruple 2-input XOR gates'},\r\n{ic:'4071',fam:'CMOS',gate:'OR',inputs:2,count:4,pkg:'14-pin DIP',vcc:'3-15V',desc:'Quadruple 2-input OR gates'},\r\n{ic:'4072',fam:'CMOS',gate:'OR',inputs:4,count:2,pkg:'14-pin DIP',vcc:'3-15V',desc:'Dual 4-input OR gates'},\r\n{ic:'4073',fam:'CMOS',gate:'AND',inputs:3,count:3,pkg:'14-pin DIP',vcc:'3-15V',desc:'Triple 3-input AND gates'},\r\n{ic:'4075',fam:'CMOS',gate:'OR',inputs:3,count:3,pkg:'14-pin DIP',vcc:'3-15V',desc:'Triple 3-input OR gates'},\r\n{ic:'4077',fam:'CMOS',gate:'XNOR',inputs:2,count:4,pkg:'14-pin DIP',vcc:'3-15V',desc:'Quadruple 2-input XNOR gates'},\r\n{ic:'4081',fam:'CMOS',gate:'AND',inputs:2,count:4,pkg:'14-pin DIP',vcc:'3-15V',desc:'Quadruple 2-input AND gates'},\r\n{ic:'4082',fam:'CMOS',gate:'AND',inputs:4,count:2,pkg:'14-pin DIP',vcc:'3-15V',desc:'Dual 4-input AND gates'},\r\n{ic:'4093',fam:'CMOS',gate:'NAND',inputs:2,count:4,pkg:'14-pin DIP',vcc:'3-15V',desc:'Quad 2-input Schmitt-trigger NAND gates'}\r\n],\r\n\r\nFAMILY_MAP:{\r\nTTL:{NAND:'7400',NOR:'7402',NOT:'7404',AND:'7408',OR:'7432',XOR:'7486'},\r\nCMOS:{NAND:'4011',NOR:'4001',NOT:'4049',AND:'4081',OR:'4071',XOR:'4070'}\r\n},\r\n\r\nLAWS:[\r\n{name:'Identity \u2014 AND',formula:'A . 1 = A',note:'Any signal AND-ed with 1 passes through unchanged.'},\r\n{name:'Identity \u2014 OR',formula:'A + 0 = A',note:'Any signal OR-ed with 0 passes through unchanged.'},\r\n{name:'Null \u2014 AND',formula:'A . 0 = 0',note:'AND with logic 0 always outputs 0, regardless of A.'},\r\n{name:'Null \u2014 OR',formula:'A + 1 = 1',note:'OR with logic 1 always outputs 1, regardless of A.'},\r\n{name:'Idempotent',formula:'A . A = A\\nA + A = A',note:'Repeating the same variable in AND or OR adds no new information.'},\r\n{name:'Complement',formula:'A . A\\' = 0\\nA + A\\' = 1',note:'A variable AND-ed with its complement is always 0; OR-ed, always 1.'},\r\n{name:'Double Negation',formula:'(A\\')\\'  = A',note:'Inverting twice returns the original signal.'},\r\n{name:'Commutative',formula:'A . B = B . A\\nA + B = B + A',note:'The order of operands around AND or OR does not change the result.'},\r\n{name:'Associative',formula:'A.(B.C) = (A.B).C',note:'Grouping parentheses can be moved freely with the same operator.'},\r\n{name:'Distributive',formula:'A.(B+C) = A.B + A.C',note:'AND distributes over OR exactly like multiplication over addition.'},\r\n{name:'Absorption',formula:'A + (A.B) = A\\nA . (A+B) = A',note:'The longer term is redundant and can be dropped without changing the output.'},\r\n{name:'De Morgan #1 \u2014 NAND',formula:'(A.B)\\' = A\\' + B\\'',note:'\"Break the bar, change the sign.\" This is why NAND is a universal gate.'},\r\n{name:'De Morgan #2 \u2014 NOR',formula:'(A+B)\\' = A\\' . B\\'',note:'The dual rule \u2014 why NOR is also universal for any Boolean function.'},\r\n{name:'Consensus Theorem',formula:'AB + A\\'C + BC = AB + A\\'C',note:'The redundant consensus term (BC) can be removed; the remaining two terms already cover it.'}\r\n],\r\n\r\nel:function(id){return document.getElementById(id);},\r\n\r\nshowToast:function(msg,type){\r\nvar t=this.el('pth-ls3-toast');\r\nif(!t)return;\r\nt.textContent=msg;\r\nt.className='pth-toast pth-show'+(type==='err'?' pth-err':type==='ok'?' pth-ok':'');\r\nvar self=this;\r\nclearTimeout(self._toastTimer);\r\nself._toastTimer=setTimeout(function(){t.className='pth-toast';},3000);\r\n},\r\n\r\nswitchTab:function(id){\r\nvar wrap=this.el('pth-ls3-wrapper');\r\nif(!wrap)return;\r\nvar btns=wrap.querySelectorAll('.pth-tab');\r\nvar panels=wrap.querySelectorAll('.pth-panel');\r\nvar i;\r\nfor(i=0;i<btns.length;i++){btns[i].classList.remove('pth-active');}\r\nfor(i=0;i<panels.length;i++){panels[i].classList.remove('pth-active');}\r\nvar btn=wrap.querySelector('[data-tab=\"'+id+'\"]');\r\nvar panel=this.el('pth-p-'+id);\r\nif(btn)btn.classList.add('pth-active');\r\nif(panel)panel.classList.add('pth-active');\r\n},\r\n\r\nKEYWORDS:{NOT:1,AND:1,NAND:1,OR:1,NOR:1,XOR:1,XNOR:1},\r\n\r\ntokenize:function(src){\r\nvar toks=[],i=0,s=src.toUpperCase().replace(\/^\\s+|\\s+$\/g,'');\r\nwhile(i<s.length){\r\nvar c=s.charAt(i);\r\nif(\/\\s\/.test(c)){i++;continue;}\r\nif(s.substr(i,4)==='XNOR'){toks.push({t:'op',v:'XNOR'});i+=4;continue;}\r\nif(s.substr(i,4)==='NAND'){toks.push({t:'op',v:'NAND'});i+=4;continue;}\r\nif(s.substr(i,3)==='NOR'){toks.push({t:'op',v:'NOR'});i+=3;continue;}\r\nif(s.substr(i,3)==='XOR'){toks.push({t:'op',v:'XOR'});i+=3;continue;}\r\nif(s.substr(i,3)==='NOT'){toks.push({t:'not'});i+=3;continue;}\r\nif(s.substr(i,3)==='AND'){toks.push({t:'op',v:'AND'});i+=3;continue;}\r\nif(s.substr(i,2)==='OR'){toks.push({t:'op',v:'OR'});i+=2;continue;}\r\nif(c==='&'||c==='*'){toks.push({t:'op',v:'AND'});i++;continue;}\r\nif(c==='+'||c==='|'){toks.push({t:'op',v:'OR'});i++;continue;}\r\nif(c==='^'){toks.push({t:'op',v:'XOR'});i++;continue;}\r\nif(c==='!'||c==='~'){toks.push({t:'not'});i++;continue;}\r\nif(c===\"'\"){toks.push({t:'post'});i++;continue;}\r\nif(c==='('){toks.push({t:'lp'});i++;continue;}\r\nif(c===')'){toks.push({t:'rp'});i++;continue;}\r\nif(c==='0'||c==='1'){toks.push({t:'const',v:c==='1'?1:0});i++;continue;}\r\nif(\/[A-Z_]\/.test(c)){\r\nvar j=i;\r\nwhile(j<s.length&&\/[A-Z0-9_]\/.test(s.charAt(j))){j++;}\r\ntoks.push({t:'var',v:s.substring(i,j)});\r\ni=j;continue;\r\n}\r\nthrow new Error('Unexpected character: '+c);\r\n}\r\nif(toks.length===0)throw new Error('Empty expression.');\r\nreturn toks;\r\n},\r\n\r\nparse:function(toks){\r\nvar pos=0;\r\nfunction peek(){return toks[pos];}\r\nfunction isOp(v){var t=peek();return t&&t.t==='op'&&t.v===v;}\r\nfunction primary(){\r\nvar t=peek(),node;\r\nif(!t)throw new Error('Unexpected end of expression.');\r\nif(t.t==='not'){pos++;node={t:'not',a:primary()};}\r\nelse if(t.t==='lp'){\r\npos++;node=orLvl();\r\nif(!peek()||peek().t!=='rp')throw new Error('Missing closing parenthesis.');\r\npos++;\r\n}\r\nelse if(t.t==='var'){pos++;node={t:'var',v:t.v};}\r\nelse if(t.t==='const'){pos++;node={t:'const',v:t.v};}\r\nelse throw new Error('Unexpected token.');\r\nwhile(peek()&&peek().t==='post'){pos++;node={t:'not',a:node};}\r\nreturn node;\r\n}\r\nfunction andLvl(){\r\nvar n=primary();\r\nwhile(isOp('AND')||isOp('NAND')){var o=peek().v;pos++;n={t:'bin',op:o,a:n,b:primary()};}\r\nreturn n;\r\n}\r\nfunction xorLvl(){\r\nvar n=andLvl();\r\nwhile(isOp('XOR')||isOp('XNOR')){var o=peek().v;pos++;n={t:'bin',op:o,a:n,b:andLvl()};}\r\nreturn n;\r\n}\r\nfunction orLvl(){\r\nvar n=xorLvl();\r\nwhile(isOp('OR')||isOp('NOR')){var o=peek().v;pos++;n={t:'bin',op:o,a:n,b:xorLvl()};}\r\nreturn n;\r\n}\r\nvar ast=orLvl();\r\nif(pos<toks.length)throw new Error('Unexpected trailing token.');\r\nreturn ast;\r\n},\r\n\r\ncollectVars:function(toks){\r\nvar seen={},out=[],i;\r\nfor(i=0;i<toks.length;i++){if(toks[i].t==='var'&&!seen[toks[i].v]){seen[toks[i].v]=1;out.push(toks[i].v);}}\r\nout.sort();\r\nreturn out;\r\n},\r\n\r\nnodeStr:function(n){\r\nif(n.t==='var')return n.v;\r\nif(n.t==='const')return String(n.v);\r\nif(n.t==='not'){return(n.a.t==='bin'?'NOT('+this.nodeStr(n.a)+')':'NOT '+this.nodeStr(n.a));}\r\nreturn this.nodeStr(n.a)+' '+n.op+' '+this.nodeStr(n.b);\r\n},\r\n\r\nnodeSym:function(n){\r\nif(n.t==='var')return n.v;\r\nif(n.t==='const')return String(n.v);\r\nif(n.t==='not'){return(n.a.t==='bin'?'('+this.nodeSym(n.a)+')\\'':(this.nodeSym(n.a)+'\\''));}\r\nvar op=n.op;\r\nif(op==='AND')op='.';\r\nif(op==='OR')op='+';\r\nif(op==='XOR')op='^';\r\nreturn this.nodeSym(n.a)+op+this.nodeSym(n.b);\r\n},\r\n\r\ndominantGate:function(n){\r\nif(n.t==='var'||n.t==='const')return'WIRE';\r\nif(n.t==='not')return'NOT';\r\nreturn n.op;\r\n},\r\n\r\ntoNANDStr:function(n,depth){\r\ndepth=depth||0;\r\nif(depth>4)return'(complex)';\r\nif(n.t==='var')return n.v;\r\nif(n.t==='const')return String(n.v);\r\nvar self=this;\r\nif(n.t==='not'){\r\nvar a=self.toNANDStr(n.a,depth+1);\r\nreturn'NAND('+a+','+a+')';\r\n}\r\nif(n.op==='AND'){\r\nvar la=self.toNANDStr(n.a,depth+1);\r\nvar lb=self.toNANDStr(n.b,depth+1);\r\nvar inner='NAND('+la+','+lb+')';\r\nreturn'NAND('+inner+','+inner+')';\r\n}\r\nif(n.op==='OR'){\r\nvar la=self.toNANDStr(n.a,depth+1);\r\nvar lb=self.toNANDStr(n.b,depth+1);\r\nreturn'NAND(NAND('+la+','+la+'),NAND('+lb+','+lb+'))';\r\n}\r\nif(n.op==='NAND')return'NAND('+self.toNANDStr(n.a,depth+1)+','+self.toNANDStr(n.b,depth+1)+')';\r\nif(n.op==='NOR'){\r\nvar la=self.toNANDStr(n.a,depth+1);\r\nvar lb=self.toNANDStr(n.b,depth+1);\r\nvar nandAB='NAND('+la+','+lb+')';\r\nvar nandAA='NAND('+la+','+la+')';\r\nvar nandBB='NAND('+lb+','+lb+')';\r\nreturn'NAND(NAND('+nandAA+','+nandBB+'),'+nandAB+')';\r\n}\r\nif(n.op==='XOR'){\r\nvar la=self.toNANDStr(n.a,depth+1);\r\nvar lb=self.toNANDStr(n.b,depth+1);\r\nvar n1='NAND('+la+','+lb+')';\r\nreturn'NAND(NAND('+la+','+n1+'),NAND('+lb+','+n1+'))';\r\n}\r\nreturn self.nodeStr(n);\r\n},\r\n\r\ntoNORStr:function(n,depth){\r\ndepth=depth||0;\r\nif(depth>4)return'(complex)';\r\nif(n.t==='var')return n.v;\r\nif(n.t==='const')return String(n.v);\r\nvar self=this;\r\nif(n.t==='not'){var a=self.toNORStr(n.a,depth+1);return'NOR('+a+','+a+')';}\r\nif(n.op==='OR'){\r\nvar la=self.toNORStr(n.a,depth+1);var lb=self.toNORStr(n.b,depth+1);\r\nvar inner='NOR('+la+','+lb+')';return'NOR('+inner+','+inner+')';\r\n}\r\nif(n.op==='AND'){\r\nvar la=self.toNORStr(n.a,depth+1);var lb=self.toNORStr(n.b,depth+1);\r\nreturn'NOR(NOR('+la+','+la+'),NOR('+lb+','+lb+'))';\r\n}\r\nif(n.op==='NOR')return'NOR('+self.toNORStr(n.a,depth+1)+','+self.toNORStr(n.b,depth+1)+')';\r\nif(n.op==='NAND'){\r\nvar la=self.toNORStr(n.a,depth+1);var lb=self.toNORStr(n.b,depth+1);\r\nvar norAB='NOR('+la+','+lb+')';\r\nreturn'NOR(NOR('+la+','+lb+'),NOR(NOR('+la+','+la+'),NOR('+lb+','+lb+')))';\r\n}\r\nif(n.op==='XOR'){\r\nvar la=self.toNORStr(n.a,depth+1);var lb=self.toNORStr(n.b,depth+1);\r\nvar n1='NOR(NOR('+la+','+la+'),NOR('+lb+','+lb+'))';\r\nvar n2='NOR('+la+','+lb+')';\r\nreturn'NOR(NOR('+n1+','+n2+'),NOR(NOR('+n1+','+n1+'),NOR('+n2+','+n2+')))';\r\n}\r\nreturn self.nodeStr(n);\r\n},\r\n\r\nmatchIC:function(gate,ninputs,family){\r\nvar db=this.IC_DB;\r\nvar fam=family||'TTL';\r\nvar candidates=[];\r\nvar i;\r\nfor(i=0;i<db.length;i++){\r\nvar ic=db[i];\r\nif(ic.fam!==fam)continue;\r\nif(ic.gate!==gate)continue;\r\nif(ic.inputs===ninputs){candidates.unshift(ic);}\r\nelse if(ic.inputs>=ninputs){candidates.push(ic);}\r\n}\r\nif(!candidates.length){\r\nvar g2=gate==='NOT'?'NOT':gate==='NAND'?'NAND':gate==='NOR'?'NOR':'AND';\r\nfor(i=0;i<db.length;i++){if(db[i].fam===fam&&db[i].gate===g2){candidates.push(db[i]);break;}}\r\n}\r\nreturn candidates.length?candidates[0]:null;\r\n},\r\n\r\ndrawPinout:function(ic,gateType,pkg){\r\nvar isHex=(gateType==='NOT'||gateType==='BUFFER');\r\nvar is16=(pkg&&pkg.indexOf('16')!==-1);\r\nvar left,right,h;\r\nif(is16){\r\nleft=['1','2','3','4','5','6','7','GND'];\r\nright=['VCC','15','14','13','12','11','10','9'];\r\nh=280;\r\n}else if(isHex){\r\nleft=['1 A1','2 Y1','3 A2','4 Y2','5 A3','6 Y3','7 GND'];\r\nright=['14 VCC','13 A6','12 Y6','11 A5','10 Y5','9 A4','8 Y4'];\r\nh=220;\r\n}else if(gateType==='NOR'){\r\nleft=['1 Y1','2 A1','3 B1','4 Y2','5 A2','6 B2','7 GND'];\r\nright=['14 VCC','13 Y4','12 A4','11 B4','10 Y3','9 A3','8 B3'];\r\nh=220;\r\n}else{\r\nleft=['1 A1','2 B1','3 Y1','4 A2','5 B2','6 Y2','7 GND'];\r\nright=['14 VCC','13 A4','12 B4','11 Y4','10 A3','9 B3','8 Y3'];\r\nh=220;\r\n}\r\nvar svg='<svg viewBox=\"0 0 200 '+(h+20)+'\" width=\"200\" height=\"'+(h+20)+'\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" role=\"img\" aria-label=\"IC pinout diagram for '+ic+'\">';\r\nsvg+='<rect x=\"60\" y=\"10\" width=\"80\" height=\"'+h+'\" fill=\"#334155\" rx=\"4\" stroke=\"#0f172a\" stroke-width=\"2\"\/>';\r\nsvg+='<rect x=\"80\" y=\"10\" width=\"40\" height=\"12\" fill=\"#fff\" rx=\"8\"\/>';\r\nsvg+='<text x=\"100\" y=\"'+(h\/2+15)+'\" font-family=\"monospace\" font-size=\"13\" font-weight=\"800\" fill=\"#fff\" text-anchor=\"middle\">'+ic+'<\/text>';\r\nvar sp=h\/(left.length);\r\nvar i;\r\nfor(i=0;i<left.length;i++){\r\nvar y=10+sp*i+sp\/2;\r\nsvg+='<line x1=\"20\" y1=\"'+y+'\" x2=\"60\" y2=\"'+y+'\" stroke=\"#94a3b8\" stroke-width=\"2.5\"\/>';\r\nsvg+='<circle cx=\"20\" cy=\"'+y+'\" r=\"3\" fill=\"#1d4ed8\"\/>';\r\nsvg+='<text x=\"25\" y=\"'+(y+4)+'\" font-family=\"monospace\" font-size=\"9\" fill=\"#1e293b\">'+left[i]+'<\/text>';\r\n}\r\nfor(i=0;i<right.length;i++){\r\nvar y=10+sp*i+sp\/2;\r\nsvg+='<line x1=\"140\" y1=\"'+y+'\" x2=\"180\" y2=\"'+y+'\" stroke=\"#94a3b8\" stroke-width=\"2.5\"\/>';\r\nsvg+='<circle cx=\"180\" cy=\"'+y+'\" r=\"3\" fill=\"#047857\"\/>';\r\nsvg+='<text x=\"136\" y=\"'+(y+4)+'\" font-family=\"monospace\" font-size=\"9\" fill=\"#1e293b\" text-anchor=\"end\">'+right[i]+'<\/text>';\r\n}\r\nsvg+='<\/svg>';\r\nreturn svg;\r\n},\r\n\r\nbuildCircuitSVG:function(ast,vars){\r\nvar self=this;\r\nfunction depth(n){\r\nif(!n||n.t==='var'||n.t==='const')return 0;\r\nif(n.t==='not')return 1+depth(n.a);\r\nreturn 1+Math.max(depth(n.a),depth(n.b));\r\n}\r\nvar d=depth(ast);\r\nif(d===0){\r\nreturn'<svg width=\"300\" height=\"80\" viewBox=\"0 0 300 80\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\"><text x=\"20\" y=\"44\" font-family=\"monospace\" font-size=\"14\" fill=\"#0f172a\">'+ast.v+'<\/text><line x1=\"60\" y1=\"40\" x2=\"260\" y2=\"40\" stroke=\"#334155\" stroke-width=\"2\"\/><text x=\"265\" y=\"44\" font-family=\"monospace\" font-size=\"14\" fill=\"#047857\">Y<\/text><\/svg>';\r\n}\r\nif(d===1){\r\nreturn self.drawSimpleGate(ast,vars);\r\n}\r\nif(d===2){\r\nreturn self.drawTwoLevel(ast,vars);\r\n}\r\nreturn self.drawComplex(ast,vars,d);\r\n},\r\n\r\ndrawSimpleGate:function(ast,vars){\r\nvar inputs=[];\r\nif(ast.t==='not'){inputs=[{label:this.nodeStr(ast.a)}];}\r\nelse if(ast.t==='bin'){inputs=[{label:this.nodeStr(ast.a)},{label:this.nodeStr(ast.b)}];}\r\nelse{inputs=[{label:this.nodeStr(ast)}];}\r\nvar gate=ast.t==='not'?'NOT':(ast.t==='bin'?ast.op:'WIRE');\r\nvar n=inputs.length;\r\nvar svgH=Math.max(120,n*56+20);\r\nvar midY=svgH\/2;\r\nvar svg='<svg viewBox=\"0 0 480 '+svgH+'\" width=\"480\" height=\"'+svgH+'\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\">';\r\nsvg+='<rect x=\"0\" y=\"0\" width=\"480\" height=\"'+svgH+'\" fill=\"#fff\"\/>';\r\nvar i,yArr=[];\r\nfor(i=0;i<n;i++){yArr.push(n===1?midY:(svgH\/(n+1))*(i+1));}\r\nfor(i=0;i<n;i++){\r\nsvg+='<line x1=\"20\" y1=\"'+yArr[i]+'\" x2=\"200\" y2=\"'+yArr[i]+'\" stroke=\"#334155\" stroke-width=\"2\"\/>';\r\nsvg+='<text x=\"12\" y=\"'+(yArr[i]-7)+'\" font-family=\"monospace\" font-size=\"12\" font-weight=\"700\" fill=\"#0f172a\">'+inputs[i].label+'<\/text>';\r\nsvg+='<circle cx=\"200\" cy=\"'+yArr[i]+'\" r=\"4\" fill=\"#1d4ed8\"\/>';\r\nsvg+='<line x1=\"200\" y1=\"'+yArr[i]+'\" x2=\"230\" y2=\"'+midY+'\" stroke=\"#334155\" stroke-width=\"2\"\/>';\r\n}\r\nsvg+='<rect x=\"230\" y=\"'+(midY-30)+'\" width=\"100\" height=\"60\" rx=\"8\" fill=\"#eff6ff\" stroke=\"#1d4ed8\" stroke-width=\"2\"\/>';\r\nsvg+='<text x=\"280\" y=\"'+(midY+6)+'\" font-family=\"monospace\" font-size=\"15\" font-weight=\"800\" fill=\"#1d4ed8\" text-anchor=\"middle\">'+gate+'<\/text>';\r\nsvg+='<line x1=\"330\" y1=\"'+midY+'\" x2=\"440\" y2=\"'+midY+'\" stroke=\"#334155\" stroke-width=\"2\"\/>';\r\nsvg+='<circle cx=\"440\" cy=\"'+midY+'\" r=\"4\" fill=\"#047857\"\/>';\r\nsvg+='<text x=\"448\" y=\"'+(midY+5)+'\" font-family=\"monospace\" font-size=\"14\" font-weight=\"800\" fill=\"#047857\">Y<\/text>';\r\nsvg+='<\/svg>';\r\nreturn svg;\r\n},\r\n\r\ndrawTwoLevel:function(ast,vars){\r\nvar self=this;\r\nfunction getLeaves(n){\r\nif(n.t==='var'||n.t==='const')return[self.nodeStr(n)];\r\nif(n.t==='not')return[self.nodeStr(n)];\r\nreturn getLeaves(n.a).concat(getLeaves(n.b));\r\n}\r\nvar leaves=getLeaves(ast);\r\nvar numL=leaves.length;\r\nvar svgH=Math.max(160,numL*52+30);\r\nvar midY=svgH\/2;\r\nvar svg='<svg viewBox=\"0 0 560 '+svgH+'\" width=\"560\" height=\"'+svgH+'\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\">';\r\nsvg+='<rect x=\"0\" y=\"0\" width=\"560\" height=\"'+svgH+'\" fill=\"#fff\"\/>';\r\nvar i,y,sp=(svgH-20)\/(numL+1);\r\nfor(i=0;i<numL;i++){\r\ny=20+sp*(i+1);\r\nsvg+='<line x1=\"10\" y1=\"'+y+'\" x2=\"160\" y2=\"'+y+'\" stroke=\"#334155\" stroke-width=\"2\"\/>';\r\nsvg+='<text x=\"5\" y=\"'+(y-7)+'\" font-family=\"monospace\" font-size=\"11\" font-weight=\"700\" fill=\"#0f172a\">'+leaves[i]+'<\/text>';\r\nsvg+='<circle cx=\"160\" cy=\"'+y+'\" r=\"3\" fill=\"#1d4ed8\"\/>';\r\nsvg+='<line x1=\"160\" y1=\"'+y+'\" x2=\"200\" y2=\"'+midY+'\" stroke=\"#94a3b8\" stroke-width=\"1.5\"\/>';\r\n}\r\nvar rootGate=ast.t==='not'?'NOT':(ast.t==='bin'?ast.op:'\u2014');\r\nsvg+='<rect x=\"200\" y=\"'+(midY-32)+'\" width=\"110\" height=\"64\" rx=\"8\" fill=\"#eff6ff\" stroke=\"#1d4ed8\" stroke-width=\"2\"\/>';\r\nsvg+='<text x=\"255\" y=\"'+(midY+6)+'\" font-family=\"monospace\" font-size=\"14\" font-weight=\"800\" fill=\"#1d4ed8\" text-anchor=\"middle\">'+rootGate+'<\/text>';\r\nsvg+='<line x1=\"310\" y1=\"'+midY+'\" x2=\"460\" y2=\"'+midY+'\" stroke=\"#334155\" stroke-width=\"2.5\"\/>';\r\nsvg+='<circle cx=\"460\" cy=\"'+midY+'\" r=\"5\" fill=\"#047857\"\/>';\r\nsvg+='<text x=\"470\" y=\"'+(midY+5)+'\" font-family=\"monospace\" font-size=\"15\" font-weight=\"800\" fill=\"#047857\">Y<\/text>';\r\nsvg+='<\/svg>';\r\nreturn svg;\r\n},\r\n\r\ndrawComplex:function(ast,vars,d){\r\nvar self=this;\r\nvar rootGate=ast.t==='not'?'NOT':(ast.t==='bin'?ast.op:'\u2014');\r\nvar svgH=Math.max(200,vars.length*48+40);\r\nvar midY=svgH\/2;\r\nvar svg='<svg viewBox=\"0 0 560 '+svgH+'\" width=\"560\" height=\"'+svgH+'\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\">';\r\nsvg+='<rect x=\"0\" y=\"0\" width=\"560\" height=\"'+svgH+'\" fill=\"#fff\"\/>';\r\nsvg+='<rect x=\"10\" y=\"'+(midY-40)+'\" width=\"160\" height=\"80\" rx=\"8\" fill=\"#f8fafc\" stroke=\"#cbd5e1\" stroke-width=\"1.5\"\/>';\r\nsvg+='<text x=\"90\" y=\"'+midY+'\" font-family=\"monospace\" font-size=\"11\" fill=\"#334155\" text-anchor=\"middle\">';\r\nfor(var i=0;i<Math.min(vars.length,5);i++){svg+=vars[i]+(i<vars.length-1?', ':'');}\r\nsvg+='<\/text>';\r\nsvg+='<text x=\"90\" y=\"'+(midY+16)+'\" font-family=\"monospace\" font-size=\"10\" fill=\"#334155\" text-anchor=\"middle\">'+vars.length+' variable(s)<\/text>';\r\nsvg+='<line x1=\"170\" y1=\"'+midY+'\" x2=\"210\" y2=\"'+midY+'\" stroke=\"#334155\" stroke-width=\"2\"\/>';\r\nsvg+='<rect x=\"210\" y=\"'+(midY-35)+'\" width=\"130\" height=\"70\" rx=\"8\" fill=\"#eff6ff\" stroke=\"#1d4ed8\" stroke-width=\"2\"\/>';\r\nsvg+='<text x=\"275\" y=\"'+(midY-8)+'\" font-family=\"monospace\" font-size=\"13\" font-weight=\"800\" fill=\"#1d4ed8\" text-anchor=\"middle\">'+rootGate+'<\/text>';\r\nsvg+='<text x=\"275\" y=\"'+(midY+10)+'\" font-family=\"sans-serif\" font-size=\"10\" fill=\"#334155\" text-anchor=\"middle\">depth '+d+'<\/text>';\r\nsvg+='<line x1=\"340\" y1=\"'+midY+'\" x2=\"460\" y2=\"'+midY+'\" stroke=\"#334155\" stroke-width=\"2.5\"\/>';\r\nsvg+='<circle cx=\"460\" cy=\"'+midY+'\" r=\"5\" fill=\"#047857\"\/>';\r\nsvg+='<text x=\"470\" y=\"'+(midY+5)+'\" font-family=\"monospace\" font-size=\"15\" font-weight=\"800\" fill=\"#047857\">Y<\/text>';\r\nsvg+='<text x=\"275\" y=\"'+(svgH-12)+'\" font-family=\"sans-serif\" font-size=\"10\" fill=\"#94a3b8\" text-anchor=\"middle\">Deeply nested \u2014 schematic shows root gate only. See full expression in Analyzer.<\/text>';\r\nsvg+='<\/svg>';\r\nreturn svg;\r\n},\r\n\r\nrunAnalysis:function(){\r\nvar self=this;\r\nvar input=this.el('pth-ls3-formula').value.replace(\/^\\s+|\\s+$\/g,'');\r\nvar errBox=this.el('pth-ls3-err');\r\nvar family=this.el('pth-ls3-family').value;\r\nerrBox.style.display='none';\r\nif(!input){errBox.textContent='Please enter a Boolean expression.';errBox.style.display='block';return;}\r\nvar toks,ast,vars;\r\ntry{\r\ntoks=this.tokenize(input);\r\nast=this.parse(toks);\r\nvars=this.collectVars(toks);\r\nif(vars.length===0)throw new Error('No variables found.');\r\nif(vars.length>8)throw new Error('Maximum 8 variables supported.');\r\n}catch(e){\r\nerrBox.textContent='Syntax error: '+e.message;\r\nerrBox.style.display='block';\r\nthis.showToast('Parse error','err');\r\nreturn;\r\n}\r\nthis.currentAST=ast;\r\nthis.currentVars=vars;\r\nvar gate=this.dominantGate(ast);\r\nvar numInputs=vars.length>1?Math.min(vars.length,4):1;\r\nif(ast.t==='bin'){numInputs=2;}\r\nvar icMatch=this.matchIC(gate,numInputs,family);\r\nvar icNum=icMatch?icMatch.ic:(family==='TTL'?this.FAMILY_MAP.TTL.AND:this.FAMILY_MAP.CMOS.AND);\r\nvar readable=this.nodeStr(ast);\r\nvar sym=this.nodeSym(ast);\r\nthis.currentFormat=readable.toLowerCase().replace(\/\\bnot\\b\/g,'not').replace(\/\\band\\b\/g,'and').replace(\/\\bor\\b\/g,'or').replace(\/\\bxor\\b\/g,'xor');\r\nthis.el('pth-r-readable').textContent=readable;\r\nthis.el('pth-r-sym').textContent=sym;\r\nthis.el('pth-r-gen').textContent=this.currentFormat;\r\nthis.el('pth-r-vars').textContent=vars.join(', ')+' ('+vars.length+')';\r\nthis.el('pth-r-gate').textContent=gate;\r\nthis.el('pth-r-ic').textContent=icNum;\r\nif(icMatch){\r\nthis.el('pth-r-gates').textContent=icMatch.desc;\r\nthis.el('pth-r-pwr').textContent=icMatch.pkg+' \/ '+icMatch.vcc;\r\nthis.el('pth-r-inputs').textContent=icMatch.inputs+' input(s) per gate';\r\nthis.el('pth-r-pinout').innerHTML=this.drawPinout(icMatch.ic,icMatch.gate,icMatch.pkg);\r\n}else{\r\nthis.el('pth-r-gates').textContent='\u2014';\r\nthis.el('pth-r-pwr').textContent='\u2014';\r\nthis.el('pth-r-inputs').textContent='\u2014';\r\nthis.el('pth-r-pinout').innerHTML='<p style=\"color:#334155;font-size:.85rem;\">IC match not found for this configuration.<\/p>';\r\n}\r\nthis.el('pth-r-nand').textContent=this.toNANDStr(ast,0);\r\nthis.el('pth-r-nor').textContent=this.toNORStr(ast,0);\r\nvar circSVG=this.buildCircuitSVG(ast,vars);\r\nthis.currentSVG=circSVG;\r\nvar circBox=this.el('pth-circuit-svg');\r\nif(circBox)circBox.innerHTML=circSVG;\r\nvar dlBtn=this.el('pth-circuit-dl');\r\nif(dlBtn)dlBtn.style.display='inline-flex';\r\nthis.el('pth-ls3-results').style.display='block';\r\nthis.el('pth-ls3-empty').style.display='none';\r\nthis.history.unshift({expr:input,ic:icNum,time:new Date().toLocaleTimeString()});\r\nif(this.history.length>12)this.history.pop();\r\nthis.renderHistory();\r\nthis.showToast('Analysis complete!','ok');\r\n},\r\n\r\nrenderICLib:function(){\r\nvar search=(this.el('pth-ic-search').value||'').toLowerCase().replace(\/^\\s+|\\s+$\/g,'');\r\nvar famF=this.el('pth-ic-family').value;\r\nvar gateF=this.el('pth-ic-gate').value;\r\nvar results=[];\r\nvar i;\r\nfor(i=0;i<this.IC_DB.length;i++){\r\nvar ic=this.IC_DB[i];\r\nif(famF!=='ALL'&&ic.fam!==famF)continue;\r\nif(gateF!=='ALL'&&ic.gate!==gateF)continue;\r\nif(search&&ic.ic.toLowerCase().indexOf(search)===-1&&ic.desc.toLowerCase().indexOf(search)===-1&&ic.gate.toLowerCase().indexOf(search)===-1)continue;\r\nresults.push(ic);\r\n}\r\nvar count=this.el('pth-ic-count');\r\nif(count)count.textContent='Showing '+results.length+' of '+this.IC_DB.length+' ICs';\r\nvar grid=this.el('pth-ic-grid');\r\nif(!grid)return;\r\nif(!results.length){grid.innerHTML='<p class=\"pth-empty\">No ICs match the current filters.<\/p>';return;}\r\nvar html='';\r\nfor(i=0;i<results.length;i++){\r\nvar ic=results[i];\r\nvar famCls=ic.fam==='TTL'?'pth-tag-ttl':'pth-tag-cmos';\r\nhtml+='<div class=\"pth-ic-card\">';\r\nhtml+='<div class=\"pth-ic-num\">'+ic.ic+'<\/div>';\r\nhtml+='<div class=\"pth-ic-desc\">'+ic.desc+'<\/div>';\r\nhtml+='<div class=\"pth-ic-meta\">';\r\nhtml+='<span class=\"pth-chip-tag '+famCls+'\">'+ic.fam+'<\/span>';\r\nhtml+='<span class=\"pth-chip-tag pth-tag-gate\">'+ic.gate+'<\/span>';\r\nhtml+='<span class=\"pth-chip-tag pth-tag-pkg\">'+ic.inputs+'-in<\/span>';\r\nhtml+='<span class=\"pth-chip-tag pth-tag-pkg\">'+ic.count+'\u00d7 gates<\/span>';\r\nhtml+='<span class=\"pth-chip-tag pth-tag-pkg\">'+ic.pkg+'<\/span>';\r\nhtml+='<span class=\"pth-chip-tag '+famCls+'\">'+ic.vcc+'<\/span>';\r\nhtml+='<\/div><\/div>';\r\n}\r\ngrid.innerHTML=html;\r\n},\r\n\r\nrenderLaws:function(){\r\nvar grid=this.el('pth-law-grid');\r\nif(!grid)return;\r\nvar html='';\r\nvar i;\r\nfor(i=0;i<this.LAWS.length;i++){\r\nvar l=this.LAWS[i];\r\nvar fmtd=l.formula.replace(\/\\n\/g,'<br>');\r\nhtml+='<div class=\"pth-law-card\">';\r\nhtml+='<div class=\"pth-law-name\">'+l.name+'<\/div>';\r\nhtml+='<div class=\"pth-law-formula\">'+fmtd+'<\/div>';\r\nhtml+='<div class=\"pth-law-note\">'+l.note+'<\/div>';\r\nhtml+='<\/div>';\r\n}\r\ngrid.innerHTML=html;\r\n},\r\n\r\nrenderHistory:function(){\r\nvar list=this.el('pth-hist-list');\r\nif(!list)return;\r\nif(!this.history.length){list.innerHTML='<div class=\"pth-empty\">No history yet \u2014 run an analysis to begin.<\/div>';return;}\r\nvar html='';\r\nvar self=this;\r\nvar i;\r\nfor(i=0;i<this.history.length;i++){\r\nvar h=this.history[i];\r\nhtml+='<div class=\"pth-hist-item\">';\r\nhtml+='<div><div class=\"pth-hist-expr\">'+h.expr.replace(\/&\/g,'&amp;').replace(\/<\/g,'&lt;')+'<\/div>';\r\nhtml+='<div class=\"pth-hist-sub\">'+h.ic+' &bull; '+h.time+'<\/div><\/div>';\r\nhtml+='<button type=\"button\" class=\"pth-hist-load\" data-expr=\"'+h.expr.replace(\/\"\/g,'&quot;')+'\">Load<\/button>';\r\nhtml+='<\/div>';\r\n}\r\nlist.innerHTML=html;\r\nvar btns=list.querySelectorAll('.pth-hist-load');\r\nfor(i=0;i<btns.length;i++){\r\nbtns[i].addEventListener('click',function(){\r\nself.el('pth-ls3-formula').value=this.getAttribute('data-expr');\r\nself.switchTab('analyzer');\r\nself.runAnalysis();\r\n});\r\n}\r\n},\r\n\r\nclearAll:function(){\r\nthis.el('pth-ls3-formula').value='';\r\nthis.el('pth-ls3-err').style.display='none';\r\nvar res=this.el('pth-ls3-results');if(res)res.style.display='none';\r\nvar emp=this.el('pth-ls3-empty');if(emp)emp.style.display='block';\r\nvar circ=this.el('pth-circuit-svg');if(circ)circ.innerHTML='<div class=\"pth-svg-empty\">Run an analysis in the Analyzer tab to generate the circuit diagram here.<\/div>';\r\nvar dl=this.el('pth-circuit-dl');if(dl)dl.style.display='none';\r\nthis.currentAST=null;this.currentSVG='';\r\nthis.showToast('Cleared','ok');\r\n},\r\n\r\ndownloadSVG:function(){\r\nif(!this.currentSVG){this.showToast('Run analysis first','err');return;}\r\nvar blob=new Blob([this.currentSVG],{type:'image\/svg+xml'});\r\nvar url=URL.createObjectURL(blob);\r\nvar a=document.createElement('a');\r\na.href=url;a.download='logic-circuit.svg';\r\ndocument.body.appendChild(a);a.click();document.body.removeChild(a);\r\nsetTimeout(function(){URL.revokeObjectURL(url);},1000);\r\nthis.showToast('SVG downloaded!','ok');\r\n},\r\n\r\ncopyFormat:function(){\r\nif(!this.currentFormat){this.showToast('Run analysis first','err');return;}\r\nvar ta=document.createElement('textarea');\r\nta.value=this.currentFormat;ta.style.position='fixed';ta.style.opacity='0';\r\ndocument.body.appendChild(ta);ta.select();\r\ntry{document.execCommand('copy');this.showToast('Copied!','ok');}\r\ncatch(e){this.showToast('Copy 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MutationObserver(function(){\r\nif(document.getElementById('pth-ls3-wrapper')){pthLS3Obs.disconnect();pthLS3Init();}\r\n});\r\npthLS3Obs.observe(document.body||document.documentElement,{childList:true,subtree:true});\r\nsetTimeout(function(){pthLS3Obs.disconnect();},10000);\r\n}\r\n})();\r\n<\/script>\n\n\n\n\n<style>\n.pth-feature-wrap{display:grid;grid-template-columns:repeat(auto-fit,minmax(280px,1fr));gap:20px;margin-bottom:40px}\n.pth-feat-box{border:1px solid #e2e8f0;background:#fff;padding:24px;border-radius:12px;box-shadow:0 4px 6px -1px rgba(0,0,0,0.02);transition:all .3s ease}\n.pth-feat-box:hover{border-color:#bfdbfe;transform:translateY(-3px);box-shadow:0 10px 15px -3px rgba(0,0,0,0.05)}\n.pth-feat-title{font-size:1.05rem;font-weight:800;color:#0f172a;margin:0 0 10px;display:flex;align-items:center;gap:10px}\n.pth-feat-text{font-size:.9rem;color:#1e293b;line-height:1.6;margin:0;font-weight:500}\n.pth-steps-wrap{border:1px solid #e2e8f0;background:#fff;padding:40px 30px;border-radius:16px;text-align:center;box-shadow:0 4px 6px -1px rgba(0,0,0,0.02);margin-bottom:40px;width:100%;box-sizing:border-box}\n.pth-steps-title{font-size:1.2rem;font-weight:800;color:#0f172a;text-transform:uppercase;margin:0 0 35px;letter-spacing:1px}\n.pth-steps-grid{display:grid;grid-template-columns:repeat(auto-fit,minmax(220px,1fr));gap:30px}\n.pth-step-item{display:flex;flex-direction:column;align-items:center}\n.pth-step-num{width:45px;height:45px;background:#2563eb;color:#fff;border-radius:50%;display:flex;align-items:center;justify-content:center;font-weight:800;font-size:1.2rem;margin-bottom:15px;box-shadow:0 4px 10px rgba(37,99,235,.3)}\n.pth-step-name{font-weight:800;color:#0f172a;margin:0 0 8px;font-size:1rem}\n.pth-step-desc{font-size:.9rem;color:#1e293b;line-height:1.5;margin:0;font-weight:500}\n<\/style>\n<div class=\"pth-feature-wrap\">\n  <div class=\"pth-feat-box\">\n    <p class=\"pth-feat-title\"><span aria-hidden=\"true\">\ud83d\udfe2<\/span> Boolean to Hardware in One Step<\/p>\n    <p class=\"pth-feat-text\">Type any Boolean expression \u2014 including NAND, NOR, and XOR operators \u2014 and the Analyzer tab returns the matching IC part number, gate configuration, pin package, and supply voltage for either the 7400 TTL or 4000 CMOS family. Switch families with the dropdown and the IC recommendation updates instantly without re-running anything.<\/p>\n  <\/div>\n  <div class=\"pth-feat-box\">\n    <p class=\"pth-feat-title\"><span aria-hidden=\"true\">\ud83d\udd35<\/span> 35-IC Searchable Library<\/p>\n    <p class=\"pth-feat-text\">The IC Library tab holds 35 integrated circuits across both families \u2014 13 TTL (7400 through 7486) and 22 CMOS (4000 through 4093). Filter by family, gate type, or search by part number to compare gate count, input count, pin package, and voltage in one place. Useful when the recommended IC is out of stock and you need a functional alternative.<\/p>\n  <\/div>\n  <div class=\"pth-feat-box\">\n    <p class=\"pth-feat-title\"><span aria-hidden=\"true\">\ud83d\udfe3<\/span> Live SVG Circuit Builder<\/p>\n    <p class=\"pth-feat-text\">Every analysis automatically draws a live SVG gate diagram in the Circuit Builder tab. Simple expressions get a clean input-to-gate-to-output schematic; compound expressions show a hierarchical two-level layout with connecting wires. The SVG downloads to your device for use in reports, lab sheets, or slide presentations without screen-capturing.<\/p>\n  <\/div>\n<\/div>\n \n<div class=\"pth-steps-wrap\">\n  <p class=\"pth-steps-title\">How to Use Digital Logic Studio Pro<\/p>\n  <div class=\"pth-steps-grid\">\n    <div class=\"pth-step-item\">\n      <div class=\"pth-step-num\" aria-hidden=\"true\">1<\/div>\n      <p class=\"pth-step-name\">Enter Your Formula<\/p>\n      <p class=\"pth-step-desc\">Type a Boolean expression in the input box \u2014 words like AND, OR, NOT, NAND, NOR, XOR all work \u2014 or tap a Quick Load tag for an instant example. Press Enter or click Analyze.<\/p>\n    <\/div>\n    <div class=\"pth-step-item\">\n      <div class=\"pth-step-num\" aria-hidden=\"true\">2<\/div>\n      <p class=\"pth-step-name\">Choose Your IC Family<\/p>\n      <p class=\"pth-step-desc\">Use the dropdown to select TTL 7400 (5V fixed rail) or CMOS 4000 (3-15V wide range). The IC recommendation, gate count, pin package, and pinout diagram all update to match your chosen family.<\/p>\n    <\/div>\n    <div class=\"pth-step-item\">\n      <div class=\"pth-step-num\" aria-hidden=\"true\">3<\/div>\n      <p class=\"pth-step-name\">Read the Results<\/p>\n      <p class=\"pth-step-desc\">The Analyzer returns the readable form, symbolic notation, generator format, dominant gate type, matched IC part number, NAND-only form, and NOR-only form. Click the pinout to see pin assignments.<\/p>\n    <\/div>\n    <div class=\"pth-step-item\">\n      <div class=\"pth-step-num\" aria-hidden=\"true\">4<\/div>\n      <p class=\"pth-step-name\">Explore Other Tabs<\/p>\n      <p class=\"pth-step-desc\">Switch to Circuit Builder for the SVG schematic, IC Library to find alternatives, Boolean Laws for the algebra reference, or History to reload any previous formula from the current session.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n\n\n<p class=\"wp-block-paragraph\">Last updated: July 2026<\/p>\n\n\n\n<h2 id=\"\ud83d\udd34-ttl-or-cmos-making-the-right-call-before-you-order-parts\" class=\"wp-block-heading\">\ud83d\udd34&nbsp;<strong>TTL or CMOS? Making the Right Call Before You Order Parts<\/strong><\/h2>\n\n\n<figure class=\"pth-article-figure pth-img-left\" style=\"float:left; width:700px; max-width:100%; margin:4px 28px 16px 0; clear:left;\"><img decoding=\"async\" src=\"https:\/\/schoolict.net\/tools\/wp-content\/uploads\/2026\/07\/digital-logic-studio-pro-ic-families-800x447.jpeg\" alt=\"Side-by-side comparison diagram showing a TTL 7408 chip at 5V and a CMOS 4081 chip at 3-15V supply range\" width=\"700\" height=\"394\" loading=\"lazy\" data-no-lazy=\"1\" class=\"pth-article-img\" style=\"width:100%;height:auto;display:block;border-radius:10px;border:1px solid #e2e8f0;\"><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\">The IC family dropdown in the Analyzer tab is not just a cosmetic toggle \u2014 it changes which chip the tool recommends, and choosing wrong means the part you order will not work with the rest of your circuit. Here is the practical breakdown.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Pick&nbsp;<strong>TTL (7400 series)<\/strong>&nbsp;when your circuit runs on a fixed 5-volt regulated supply and you are working with classic classroom hardware, breadboard lab kits, or any project that already uses 5V logic throughout. TTL chips switch fast, are extremely well-documented, and a datasheet for the 7408 quad AND gate has not changed materially since 1972. The 7400, 7408, and 7404 are three chips every electronics bench should have in a drawer.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Pick&nbsp;<strong>CMOS (4000 series)<\/strong>&nbsp;when your supply voltage is anything other than a steady 5V, when the circuit runs from batteries, when power consumption matters, or when you need to interface with 3.3V microcontrollers. The 4011 (NAND) and 4071 (OR) run comfortably anywhere from 3V to 15V and draw near-zero static current. A coin-cell LED driver built around CMOS can survive weeks; the TTL equivalent would flatten the battery in hours.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">One situation students regularly get wrong: mixing TTL and CMOS in the same circuit. A TTL gate output driving a CMOS input usually works, but a CMOS output at 15V driving a TTL input rated for 5V will kill the TTL chip immediately. Keep families separate unless you have a buffer IC (like the 4050) specifically designed for level shifting between them.<\/p>\n\n\n\n<h2 id=\"\ud83d\udfe1-what-the-pinout-diagram-is-actually-showing-you\" class=\"wp-block-heading\">\ud83d\udfe1&nbsp;<strong>What the Pinout Diagram Is Actually Showing You<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">The Analyzer tab draws a simplified DIP (Dual Inline Package) pinout whenever an IC match is found. Reading it takes about thirty seconds once you know the convention, and it applies to almost every 7400 and 4000 series chip you will encounter.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>\ud83d\udd35 The\u00a0<strong>notch or dot<\/strong>\u00a0marks pin 1 \u2014 always at the top-left when the chip is oriented with the notch facing toward you.<\/li>\n\n\n\n<li>\ud83d\udfe0 Pins\u00a0<strong>number counter-clockwise<\/strong>\u00a0around the package: down the left side, then up the right side.<\/li>\n\n\n\n<li>\ud83d\udfe3 The\u00a0<strong>bottom-left pin<\/strong>\u00a0is always GND (ground). The\u00a0<strong>top-right pin<\/strong>\u00a0is always VCC (positive supply). These are the same on almost every 14-pin DIP logic chip.<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">For the quad 2-input AND (7408), pins 1-2 are the two inputs to gate 1, pin 3 is gate 1&#8217;s output, pins 4-5 are gate 2&#8217;s inputs, pin 6 is gate 2&#8217;s output \u2014 and the same pattern repeats for gates 3 and 4 on the opposite side of the chip. Once you see this layout on the 7408, you will immediately recognize the same four-gate arrangement on the 7400, 7402, 7432, and 7486. The pinout diagram here is for orientation \u2014 always pull the manufacturer&#8217;s datasheet before soldering a physical board.<\/p>\n\n\n\n<h2 id=\"\ud83d\udfe2-why-nand-and-nor-conversions-appear-on-every-analyzer-result\" class=\"wp-block-heading\">\ud83d\udfe2&nbsp;<strong>Why NAND and NOR Conversions Appear on Every Analyzer Result<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Every Analyzer result includes both a NAND-only and a NOR-only form of your expression. This is not just academic \u2014 it is genuinely useful in three real situations.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Single-chip builds:<\/strong>&nbsp;If you need both an AND function and an OR function but only want to order one chip type, you can implement both using NAND gates from a single 7400. The NAND conversion tells you exactly what to wire. For (A AND B): connect the NAND output back to itself as a second input to get NOT(NAND), which equals AND. It takes one extra gate but keeps your BOM (bill of materials) to one line item.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Exam verification:<\/strong>&nbsp;A common digital logic exam question asks you to prove De Morgan&#8217;s theorem by implementing NOT(A AND B) using only NOR gates. The NOR-only conversion in the tool shows the answer immediately, but more importantly shows the structure \u2014 which helps when the exam asks you to draw the gates, not just write the expression.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>FPGA synthesis:<\/strong>&nbsp;Modern FPGA tools convert all logic to NAND-NAND or NOR-NOR networks during technology mapping because CMOS transistor pairs implement NAND naturally. Understanding what the tool generates here gives you a window into what your synthesis tool is doing under the hood. For a deeper step-by-step simplification, take the expression to the&nbsp;<a href=\"https:\/\/schoolict.net\/tools\/boolean-expression-simplifier\/\">Boolean Expression Simplifier<\/a>&nbsp;to see each Boolean law applied in sequence.<\/p>\n\n\n\n<h2 id=\"\ud83d\udd34-reading-the-circuit-builder-diagram\" class=\"wp-block-heading\">\ud83d\udd34&nbsp;<strong>Reading the Circuit Builder Diagram<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Simple formulas \u2014 a single AND, OR, NOT, or one-level compound expression \u2014 produce a clean schematic: inputs on the left, a labeled gate rectangle in the middle, and the output labeled Y on the right. Connecting wires run left to right and meet at the gate inputs.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">For two-level expressions like (A AND B) OR C, the diagram adds a second column: all leaf terms fan into the center gate, which feeds the output. The more complex the expression, the deeper the hierarchy. Formulas with more than three levels of nesting show a simplified summary view noting the root gate type and expression depth \u2014 at that point, the full schematic is impractical to read in a browser window, and you would normally use a dedicated EDA (Electronic Design Automation) tool to generate the full net list. Download the SVG using the button below the diagram to embed it directly into a lab report or slideshow without re-screenshotting every time the formula changes.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">For truth table analysis, equivalence checking, or generating Verilog HDL from your expression, use the&nbsp;<a href=\"https:\/\/schoolict.net\/tools\/truth-table-generator\/\">Truth Table Studio Pro<\/a>. For visual K-map grouping and Quine-McCluskey minimization, the&nbsp;<a href=\"https:\/\/schoolict.net\/tools\/advanced-k-map-solver\/\">K-Map Solver Pro<\/a>&nbsp;handles 2 to 5 variables with prime implicant visualization.<\/p>\n\n\n\n<h2 id=\"\ud83d\udfe1-getting-the-most-from-the-ic-library-tab\" class=\"wp-block-heading\">\ud83d\udfe1&nbsp;<strong>Getting the Most from the IC Library Tab<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">The IC Library lists 35 chips across both families, filterable by gate type and searchable by part number or description. A few practical uses:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>\ud83d\udd35\u00a0<strong>Finding a 3-input alternative:<\/strong>\u00a0The Analyzer recommends the 2-input variant for most formulas. If your design actually has three inputs to a single AND gate, filter by &#8220;AND&#8221; and look for the 7411 (TTL) or 4073 (CMOS) \u2014 both are triple 3-input AND chips.<\/li>\n\n\n\n<li>\ud83d\udfe0\u00a0<strong>Sourcing a substitute:<\/strong>\u00a0The 4069 and 4049 both invert \u2014 but the 4049 is rated for level-shifting from higher voltages down to 5V, while the 4069 is a standard-rail inverter. If your distributor is out of the 4049, the library description flags this distinction clearly.<\/li>\n\n\n\n<li>\ud83d\udfe3\u00a0<strong>Comparing gate density:<\/strong>\u00a0The 7430 fits a full 8-input NAND gate in a single 14-pin DIP package. If your address decoder uses an 8-line AND, one 7430 replaces what would otherwise require three cascaded 7408 chips. Search &#8220;8&#8221; in the library to pull it up immediately.<\/li>\n<\/ul>\n\n\n\n\n<style>\n.pth-faq-section{margin-top:50px;margin-bottom:40px;font-family:inherit}\n.pth-faq-header{font-size:1.8rem;font-weight:800;color:#0f172a;margin-bottom:25px;border-bottom:2px solid #e2e8f0;padding-bottom:10px;display:flex;align-items:center;gap:10px}\n.pth-faq-grid{display:grid;grid-template-columns:100%;gap:20px}\n@media(min-width:768px){.pth-faq-grid{grid-template-columns:repeat(2,1fr)}}\n@media(min-width:1024px){.pth-faq-grid{grid-template-columns:repeat(3,1fr)}}\n.pth-faq-card{background:#f8fafc;padding:24px;border-radius:12px;border:1px solid #e2e8f0;transition:transform .2s ease;break-inside:avoid}\n.pth-faq-card:hover{transform:translateY(-3px);box-shadow:0 4px 12px rgba(0,0,0,.05)}\n.pth-faq-q{color:#0f172a;font-size:1rem;font-weight:700;margin:0 0 12px;line-height:1.4}\n.pth-faq-a{margin:0;font-size:.95rem;color:#1e293b;line-height:1.6;font-weight:500}\n<\/style>\n<div class=\"pth-faq-section\">\n  <div class=\"pth-faq-header\">\u2753 Frequently Asked Questions<\/div>\n  <div class=\"pth-faq-grid\">\n    <div class=\"pth-faq-card\">\n      <p class=\"pth-faq-q\">What&#8217;s the difference between the 7400 and 4011 NAND chips?<\/p>\n      <p class=\"pth-faq-a\">Both contain four 2-input NAND gates in a 14-pin DIP package \u2014 they are functionally identical in logic. The 7400 is TTL, running only on 5V with fast switching. The 4011 is CMOS, running on 3V to 15V with far lower power draw. Use the dropdown to switch between them and the pinout redraws.<\/p>\n    <\/div>\n    <div class=\"pth-faq-card\">\n      <p class=\"pth-faq-q\">Why does the tool always show NAND and NOR forms even for simple AND formulas?<\/p>\n      <p class=\"pth-faq-a\">Because NAND and NOR are universal \u2014 any gate can be built from them. The conversions appear every time because the most common reason engineers want them is precisely for simple expressions where they want to consolidate to one chip type. Complex formulas make this obvious; simple ones are where it saves the most board space.<\/p>\n    <\/div>\n    <div class=\"pth-faq-card\">\n      <p class=\"pth-faq-q\">Can I paste the generator format directly into another tool?<\/p>\n      <p class=\"pth-faq-a\">Yes. The generator format is a lowercase version of your expression using words (and, or, not) rather than symbols, compatible with Boolean expression parsers, simulation tools, and the <a href=\"\/boolean-expression-simplifier\/\" style=\"color:#1d4ed8;font-weight:700;\">Boolean Expression Simplifier<\/a> on this site. Copy it with one click from the Analyzer tab.<\/p>\n    <\/div>\n    <div class=\"pth-faq-card\">\n      <p class=\"pth-faq-q\">The recommended IC has 4 gates per package but I only need 1. Is that a problem?<\/p>\n      <p class=\"pth-faq-a\">Not at all \u2014 this is normal for DIP logic ICs. Just leave the unused gate inputs tied to a defined logic level (GND for CMOS NAND, VCC for CMOS NOR) rather than floating. A floating input on a CMOS chip picks up noise and can oscillate unpredictably.<\/p>\n    <\/div>\n    <div class=\"pth-faq-card\">\n      <p class=\"pth-faq-q\">Where can I verify truth table outputs for a formula I analyzed here?<\/p>\n      <p class=\"pth-faq-a\">Take the expression straight to the <a href=\"\/truth-table-generator\/\" style=\"color:#1d4ed8;font-weight:700;\">Truth Table Studio Pro<\/a>. It evaluates every input combination, shows intermediate sub-expression columns, and generates Verilog HDL you can load into DigitalJS to watch the gates toggle in real time.<\/p>\n    <\/div>\n    <div class=\"pth-faq-card\">\n      <p class=\"pth-faq-q\">How do I find a 3-input OR gate in the IC Library?<\/p>\n      <p class=\"pth-faq-a\">Open the IC Library tab, set the gate type filter to OR, and look for the 4075 (CMOS triple 3-input OR). There is no 7400-series 3-input OR with four gates in one package \u2014 the closest is the 7432 (2-input), so for 3-input OR you would cascade two 7432 gates or switch to CMOS.<\/p>\n    <\/div>\n    <div class=\"pth-faq-card\">\n      <p class=\"pth-faq-q\">Does the SVG circuit diagram update automatically?<\/p>\n      <p class=\"pth-faq-a\">Yes. Every time you run an analysis in the Analyzer tab, the Circuit Builder tab regenerates the SVG immediately. Switch tabs and it is already there \u2014 no separate button to press. If the expression is deeply nested, the diagram shows a simplified summary view with the root gate and expression depth labeled.<\/p>\n    <\/div>\n    <div class=\"pth-faq-card\">\n      <p class=\"pth-faq-q\">What is the 4093 in the CMOS library and when would I use it?<\/p>\n      <p class=\"pth-faq-a\">The 4093 is a quad 2-input Schmitt-trigger NAND. A Schmitt trigger adds hysteresis \u2014 the switching threshold for a rising signal is higher than for a falling one. This makes it ideal for cleaning up slow or noisy signals like those from RC circuits, push buttons, and capacitive sensors, where a standard NAND would oscillate at the threshold.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n \n","protected":false},"excerpt":{"rendered":"<p>Digital Logic Studio Pro Use Digital Logic Studio Pro to convert Boolean formulas to 7400\/4000 series ICs, generate NAND\/NOR universal forms and visualize SVG circuit diagrams \u2014 100% offline. \ud83d\udfe2 Boolean to Hardware in One Step Type any Boolean expression \u2014 including NAND, NOR, and XOR operators \u2014 and the Analyzer tab returns the matching &#8230; <a title=\"7400 Series IC Finder &amp; Digital Logic Studio Pro\" class=\"read-more\" href=\"https:\/\/schoolict.net\/tools\/7400-series-ic-finder\/\" aria-label=\"Read more about 7400 Series IC Finder &amp; Digital Logic Studio Pro\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":211,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-210","page","type-page","status-publish","has-post-thumbnail"],"_links":{"self":[{"href":"https:\/\/schoolict.net\/tools\/wp-json\/wp\/v2\/pages\/210","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/schoolict.net\/tools\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/schoolict.net\/tools\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/schoolict.net\/tools\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/schoolict.net\/tools\/wp-json\/wp\/v2\/comments?post=210"}],"version-history":[{"count":0,"href":"https:\/\/schoolict.net\/tools\/wp-json\/wp\/v2\/pages\/210\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/schoolict.net\/tools\/wp-json\/wp\/v2\/media\/211"}],"wp:attachment":[{"href":"https:\/\/schoolict.net\/tools\/wp-json\/wp\/v2\/media?parent=210"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}